Design of Phase Detector Circuit Using Op Amp

Electronic Circuits: Linear/Analog

Louis E. FrenzelJr., in Electronics Explained (Second Edition), 2018

Phase Detector

A phase detector is a mixer-like circuit that puts out a signal that is proportional to the phase difference between two input signals of the same frequency. See Fig. 4.18. A phase shift is a time difference between two signals of the same frequency. We sometimes need to know how much phase shift is present. The phase detector produces a series of output pulses whose width is proportional to the phase difference. Passing the pulses through a LPF smoothes them into a proportional DC voltage.

Figure 4.18. Phase detector converts phase shift into proportional DC average.

Filtering Pulses Into DC

A common occurrence in electronic circuits is the filtering of pulses into a DC voltage. You saw this back in Fig. 3.15 where positive pulses from a sine wave rectifier are smoothed into a near constant DC voltage. It is the capacitor that charges up and stores the pulse voltage. Then between pulses the capacitor discharges into the load maintaining a near constant DC voltage. The LPF usually includes a capacitor so performs the same function in the phase detector of Fig. 4.18. The output is a proportional average DC output.

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Low-noise oscillator design

Clive Poole , Izzat Darwazeh , in Microwave Active Circuit Analysis and Design, 2016

16.7.2 The Phase Detector Method

The basic phase detector method is shown in Figure 16.12. At the heart of this method is the phase detector. Two sources, at the same frequency and in phase quadrature, are presented to a double-balanced mixer which, together with a low-pass filter, acts as a phase detector. The difference frequency emerging from the low-pass filter has an average voltage level of 0   V. Riding on this DC signal are AC voltage fluctuations proportional to the combined phase noise of the two sources. The baseband signal is amplified and then fed into a baseband spectrum analyzer.

Figure 16.12. Phase-noise measurement: phase detector method.

In order for this method to work, phase quadrature between the oscillator under test and the reference oscillator must be strictly maintained. This is achieved by making the frequency of the reference oscillator electronically tunable and driving this from a quadrature detector connected to the output of the phase detector.

Any phase deviation from quadrature between the two sources will result in a corresponding voltage fluctuation at the output and a value other than zero. This will interfere with the measurement.

The phase detector method requires a reference source that has a lower phase noise than the oscillator being measured, and measurements made inside the loop bandwidth of the system require special correction. This means that the phase detector method is complex and requires very high-quality equipment.

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Optical System Performance Measurements

Rongqing Hui , Maurice O'Sullivan , in Fiber Optic Measurement Techniques, 2009

5.4.2.2 Jitter Measurement Based on a Phase Detector

A phase detector is basically an RF mixer that multiplies the two input signals and yields their product. Figure 5.4.7 shows the block diagram of jitter measurement setup based on a phase detector. This setup measures the fundamental clock component of the jittered waveform and compares it with a jitter-free reference clock in an RF mixer. Assume that the recovered clock from the jittered waveform is $S_J(t)=A_J\text{sin}\left[2\pi R_{b}t+\Delta \phi (t)\right]$ , where R_b is the data rate and Δφ(t) is the phase jitter. A reference clock at the same fundamental frequency $S_R(t)=A_R\text{sin}\left(2\pi R_{b}t+{\phi }_0\right)$ is used for the detection, where φ₀ is a fixed phase delay. The recovered clock and the reference mix at the phase detector, which is an RF mixer, and the output voltage is

Figure 5.4.7. Time-jitter measurement based on phase detection.

(5.4.4) $\begin{array}{ll}V(t)& =K{S}_J(t)\cdot S_R(t)\\ & =\frac{1}{2}K{A}_R{A}_J\left\{sin\left[4\pi R_{b}t+\Delta \phi (t)+{\phi }_0\right]+\text{sin}[\Delta \phi (t)-{\phi }_0]\right\}\end{array}$

where K is the efficiency of the RF mixer.

The lowpass filter removes the double-frequency component. Suppose the phase noise is small enough such that $\left|\Delta \phi (t)-{\phi }_0\right|\ll \pi$ ; the voltage signal at the filter output is approximately

(5.4.5) $V(t)\approx 0.5K{A}_R{A}_J\left[\Delta \phi (t)-{\phi }_0\right]$

This voltage signal is linearly proportional to the phase term Δφ(t), which is related to the time jitter Δt(t) through Equation 5.4.2. This voltage signal is usually much slower than the fundamental clock and can be easily digitized and analyzed with digital signal processing. The distinct advantage of the phase detection technique is the capability of measuring jitter information in real time, which allows the frequency analysis of time jitter.

The jittered waveform $S_J(t)=A_J\text{sin}\left[2\pi R_{b}t+\Delta \phi (t)\right]$ can also be characterized by a spectrum analyzer. In fact, the spectrum of the jittered signal S_J (t) should have a strong fundamental frequency component and phase modulation sidebands. The power density of the phase modulation sideband normalized by the power of the carrier should provide the magnitude as well as the frequency of the jitter. However, due to the limitation of spectral resolution and the dynamic range of a practical spectrum analyzer, the powerful carrier at frequency R_b may influence the measurement of the relatively weak phase modulation sidebands. This is especially problematic for low-frequency jitter components for which the frequency separation between the carrier and the modulation sideband is small.

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Interference into Circuits

Reinaldo Perez , in Wireless Communications Design Handbook, 1998

3.14 Phase Detectors

An ideal phase detector produces an output signal whose DC value is linearly proportional to the difference between the phases of two periodic inputs,

(3.47) $V_{\mathrm{out}}=K_{\mathrm{p}\mathrm{d}}\mathrm{\Delta }\varphi \text{,}$

where K _pd is the gain of the phase detector (V/rad) and Δϕ is the input phase difference.

The phase detector (Figure 3.57) generates an output pulse whose width is equal to the time difference between consecutive zero crossings of the two inputs f ₁(t) and f ₂(t). The two frequencies cause the phase difference to be a beat behavior. A commonly used phase detector is a multiplier. For two signals X ₁(t)   = A ₁ cos ω ₁ t and X ₂(t)   = A ₂ cos (ωt  +   Δϕ), an amplifier generates

Figure 3.57. Phase detector illustration.

(3.48) $\begin{array}{l}y\left(t\right)=\alpha A_1\cos {\omega }_{1}t{A}_2\cos \left({\omega }_{2}t+\mathrm{\Delta }\varphi \right)\\ =\frac{\alpha A_1{A}_2}{2}\cos \left[\left({\omega }_1+{\omega }_2\right)t+\mathrm{\Delta }\varphi \right]+\frac{\alpha A_1{A}_2}{2}\cos \left[\left({\omega }_1-{\omega }_2\right)t-\mathrm{\Delta }\varphi \right]\text{,}\end{array}$

where α is a proportionality constant. Thus, for ω ₁  = ω ₂, the phase voltage characteristic is

(3.49) $y\left(t\right)=\frac{\alpha A_1{A}_2}{2}\cos \mathrm{\Delta }\varphi \text{,}$

which is equal to Equation(3.47) if

$K_{\mathrm{p}\mathrm{d}}=-\frac{\alpha A_1{A}_2}{2}\text{.}$

The average output is zero if ω ₁≠   ω ₂.

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Nonlinear analysis and design of oscillator circuits

A. Suarez , ... F. Ramirez , in Microwave Wireless Communications, 2016

3.10.2 PLL Formulation

The entire analysis presented here is applicable regardless of the type of PD (analogue or digital). However, for simplicity, a PD of mixer type will be considered. For other PDs, such as tri-stage phase-frequency comparator, convenient behavioral models such as those in Refs. [42,46,47] should be introduced in the formulation. In the case of a mixer PD, the low frequency component of the output signal has the form:

(3.96) $u\left(t\right)=K_{\mathrm{d}}sin\left({\omega }_{i}t-\frac{{\theta }_{\mathrm{o}}\left(t\right)}{N}\right)=K_{\mathrm{d}}sin\varphi ,\varphi ={\omega }_{i}t-\frac{{\theta }_{\mathrm{o}}\left(t\right)}{N}$

where ${\omega }_i=2\pi f_i$ is the reference frequency, θ _o(t) is the VCO instantaneous output phase, N is the division order, and ϕ(t) is the phase-error variable. The influence of the high frequency component of the PD output has been neglected due to the presence of the loop filter. Note that the observation node considered in the admittance model (3.95) may be different from the oscillator output node. In that case, a constant phase shift Δφ will exist between the two nodes, such that:

(3.97) ${\theta }_{\mathrm{o}}\left(t\right)={\theta }_n\left(t\right)+\mathrm{\Delta }\phi$

In order to simplify the formulation, without loss of generality, it will be assumed that an offset voltage V _T ⁰ is added to the filter output to bias the VCO. Then, according to Eq. (3.94), the filter output voltage agrees with the perturbation variable ΔV _T(t). Here, the following first-order filter will be considered:

(3.98) $F\left(s\right)=\frac{{\tau }_{1}s+1}{{\tau }_{2}s+1}=\frac{\mathrm{\Delta }{V}_{\mathrm{T}}\left(s\right)}{u\left(s\right)}$

Combining the Eqs. (3.95)–(3.98), the system of differential equations governing the PLL dynamics is:

(3.99) $\begin{array}{l}{\tau }_1{K}_{\mathrm{d}}\dot{\varphi }cos\varphi +K_{\mathrm{d}}sin\varphi ={\tau }_2\mathrm{\Delta }{\dot{V}}_{\mathrm{T}}+\mathrm{\Delta }{V}_{\mathrm{T}},\\ Y_{V_{\mathrm{T}}}\mathrm{\Delta }{V}_{\mathrm{T}}+Y_V\mathrm{\Delta }V+Y_{\omega }\left(N{\omega }_i-{\omega }_{\mathrm{o}}-N\dot{\varphi }-\mathrm{j}\frac{\mathrm{\Delta }\dot{V}}{V_1}\right)=0\end{array}$

System (3.99) is composed by three real nonlinear differential equations in the state variables (ϕ,   ΔV,   ΔV _T), because the admittance equation is complex. It can be written in a matrix form as:

(3.100) $M_{\dot{X}}\dot{\overline{x}}\left(t\right)+M_X\overline{x}\left(t\right)+\overline{G}\left[\overline{x}\left(t\right)\right]=\overline{0},\overline{x}={\left(\varphi ,\mathrm{\Delta }V,\mathrm{\Delta }{V}_{\mathrm{T}}\right)}^t$

with:

(3.101) $M_{\dot{X}}=\left(\begin{array}{ccc}\hfill {\tau }_1{K}_{\mathrm{d}}cos\varphi \hfill & \hfill 0\hfill & \hfill -{\tau }_2\hfill \\ \hfill -N{Y}_{\omega }^{\mathrm{r}}\hfill & \hfill Y_{\omega }^{\mathrm{i}}/V_1\hfill & \hfill 0\hfill \\ \hfill -N{Y}_{\omega }^{\mathrm{i}}\hfill & \hfill Y_{\omega }^{\mathrm{r}}/V\hfill & \hfill 0\hfill \end{array}\right),M_X=\left(\begin{array}{ccc}\hfill 0\hfill & \hfill 0\hfill & \hfill -1\hfill \\ \hfill 0\hfill & \hfill Y_V^{\mathrm{r}}\hfill & \hfill Y_{V_{\mathrm{T}}}^{\mathrm{r}}\hfill \\ \hfill 0\hfill & \hfill Y_V^{\mathrm{i}}\hfill & \hfill Y_{V_{\mathrm{T}}}^{\mathrm{i}}\hfill \end{array}\right),\overline{G}=\left(\begin{array}{c}\hfill K_{\mathrm{d}}sin\varphi \hfill \\ \hfill Y_{\omega }^{\mathrm{r}}\left(N{\omega }_{\mathrm{i}}-{\omega }_{\mathrm{o}}\right)\hfill \\ \hfill Y_{\omega }^{\mathrm{i}}\left(N{\omega }_{\mathrm{i}}-{\omega }_{\mathrm{o}}\right)\hfill \end{array}\right)$

where the superindexes r and i mean real and imaginary parts. Then, Eq. (3.99) can be expressed in the following compact form:

(3.102) $\dot{\overline{x}}\left(t\right)=-M_{\dot{X}}^{-1}\left\{M_X\overline{x}\left(t\right)+\overline{G}\left[\overline{x}\left(t\right)\right]\right\}=\overline{f}\left[\overline{x}\left(t\right)\right]$

System (3.102) can be used to simulate the evolution of the PLL variables during the transient to phase-locked state. The phase-locked solution is an EP of system (3.102), which is given by:

(3.103) $\dot{\overline{x}}\left(t\right)=\overline{f}\left[\overline{x}\left(t\right)\right]=\overline{0}\to \overline{x}\left(t\right)={\overline{x}}_0$

Note that $\dot{\overline{x}}\left(t\right)=\overline{0}$ implies that the phase-locked solution ${\overline{x}}_0$ has constant frequency and amplitude. System (3.103) allows the prediction of the variation of the phase-locked solution amplitude with the reference frequency or any other parameter.

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Frequency definition and estimation in modern power systems

Álvaro Ortega Manjavacas , Federico Milano , in Converter-Based Dynamics and Control of Modern Power Systems, 2021

Synchronous reference frame PLL

Fig. 6.8 shows the commonly used SRF-PLL, where the PD includes a constant delay τ _θ (hence ${\tilde{\theta }}_i(t)={\theta }_i(t-{\tau }_{\theta })$ ); and the LF consists of a proportional integral (PI) regulator.

Fig. 6.8. Scheme of an SRF-PLL [32].

The equations that represent the SRF-PLL shown in Fig. 6.8 are:

(6.18) $\begin{array}{l}{T}_{2,\text{LF}}{\stackrel{.}{x}}_i(t)={ϵ}_{\theta }(t)={\theta }_i(t-{\tau }_{\theta })-{\tilde{\theta }}_{i,\text{dq}}(t),\\ T_{1,\text{LF}}{\stackrel{.}{x}}_i(t)=\mathrm{\Delta }{\tilde{\omega }}_i(t)-x_i(t),\\ {\stackrel{.}{\stackrel{~}{\theta }}}_{i,\text{dq}}(t)=K_{\text{VCO}}\mathrm{\Delta }{\tilde{\omega }}_i(t),\\ 0={\tilde{\omega }}_i(t)-({\omega }^{\text{ref}}+\mathrm{\Delta }{\tilde{\omega }}_i(t)),\end{array}$

where ω ^ref can either be the synchronous frequency ω _o = 1 pu, or the frequency of the CoI.

Eq. (6.13) can be thus rewritten taking into account the transient effect of the SRF-PLL, as follows:

(6.19) $\begin{array}{l}\hfill v_{i,\text{d}}(t)+j{v}_{i,\text{q}}(t)=v_i(t)(-sin({ϵ}_{\theta }(t))+jcos({ϵ}_{\theta }(t))).\end{array}$

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Synchronization

Ali Grami , in Introduction to Digital Communications, 2016

8.3.1 Basic Operation

As shown in Figure 8.3, a generic PLL consists of three major components: a phase detector , a loop filter , and a voltage-controlled oscillator (VCO) . Because of the multiplier, the circuit is nonlinear and thus difficult to analyze, as the Fourier transform cannot be easily employed. Hence, the analysis is in the time domain. The VCO is a sinusoidal oscillator whose frequency is linearly controlled by a voltage applied to it from an external source (the PLL output); in a way, any analog frequency modulator can function as a VCO. The multiplier simply produces a measure of the difference in phase between an incoming sinusoidal signal and the local replica produced by the VCO. As the received signal and the local replica change with respect to each other, the phase difference (or error) becomes a time-varying signal that is sent into the loop filter. The loop filter, which is a low-pass filter, removes high-frequency components and governs the PLL's response to variations in the error signal.

Figure 8.3. Basic components of a phase-locked loop.

The goal is to generate a VCO output whose frequency is the same as the frequency of the received signal and phase is different from the phase of the received signal by 90 degrees. Phase lock is achieved by feeding a filtered version of a signal, which consists of the phase difference between the received signal and the VCO output, back to the input of the VCO. The VCO adjusts its own frequency such that its frequency and phase can track those of the PLL input signal. The received sinusoidal signal (i.e., the PLL input) is defined as follows:

(8.4) $s\left(t\right)=A_{i}sin\left(2\pi f_{c}t+{\theta }_i\left(t\right)\right)$

where A _i and f _c represent the amplitude and frequency, respectively, and θ _i (t) is a slowly-varying phase. The PLL output provides the control voltage for the VCO. The output of the VCO is defined by

(8.5) $y\left(t\right)=A_{o}cos\left(2\pi f_{c}t+{\theta }_o\left(t\right)\right)$

where A _o and f _c are the amplitude and frequency, respectively, and θ _o (t) represents the estimate of θ _i (t). The phase error is thus defined as follows:

(8.6) ${\theta }_e\left(t\right)={\theta }_i\left(t\right)-{\theta }_o\left(t\right)={\theta }_i\left(t\right)-2\pi k{\displaystyle \underset{0}{\overset{t}{\int }}}v\left(s\right)ds$

where v(t) is the VCO input (i.e., PLL output) and k is a constant representing the frequency sensitivity of the VCO. With s(t) and y(t) as the inputs to the multiplier with a gain of m, the output of the multiplier is then as follows:

(8.7) $\mathit{ms}\left(t\right)y\left(t\right)=m\left(A_{i}sin\left(2\pi f_{c}t+{\theta }_i\left(t\right)\right)\right)\left(A_{o}cos\left(2\pi f_{c}t+{\theta }_o\left(t\right)\right)\right)$

After using a trigonometric identity to transform the product of two sinusoids into the sum of two sinusoids, it becomes obvious that the output of the multiplier has a high-frequency component and a low-frequency component, as follows:

(8.8) $\mathit{ms}\left(t\right)y\left(t\right)=\left(\frac{m{A}_i{A}_o}{2}\right)\left(sin\left(4\pi f_{c}t+{\theta }_i\left(t\right)+{\theta }_o\left(t\right)\right)+sin\left({\theta }_i\left(t\right)-{\theta }_o\left(t\right)\right)\right)$

Since the high-frequency term is suppressed by the loop filter, we could assume the effective input to the loop filter is in fact the low-frequency term. The error signal e(t), which is the input to the loop filter, is then considered as follows:

(8.9) $e\left(t\right)=\left(\frac{m{A}_i{A}_o}{2}\right)sin\left({\theta }_e\left(t\right)\right)$

The error signal is solely a function of the difference of the phase of the PLL input and the phase of the VCO output. With h(t) as the impulse response of the loop filter, the output of the PLL v(t) is then defined by the following convolution:

(8.10) $v\left(t\right)=e\left(t\right)*h\left(t\right)=\left(\frac{m{A}_i{A}_o}{2}\right){\displaystyle \underset{-\infty }{\overset{t}{\int }}}sin\left({\theta }_e\left(\tau \right)\right)h\left(t-\tau \right)d\tau$

where * denotes the convolution operation. If we substitute (8.10) into (8.6), we then end up with a double integral. To avoid the complexity of a double integral, we first differentiate (8.6) and then use (8.10) to obtain the following nonlinear integro-differential equation describing the dynamic PLL behavior:

(8.11) $\frac{d{\theta }_e\left(t\right)}{dt}=\frac{d{\theta }_i\left(t\right)}{dt}-2\pi C{\displaystyle \underset{-\infty }{\overset{t}{\int }}}sin\left({\theta }_e\left(\tau \right)\right)h\left(t-\tau \right)d\tau$

where $C=m{A}_i{A}_{o}k/2$ is the loop-gain parameter.

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Complex Electronic System Design Example

Peter Wilson , H. Alan Mantooth , in Model-Based Engineering for Complex Electronic Systems, 2013

13.4.5.2 Level 0 Phase Locked Loop

This model represents the control system portion of a linear phase locked loop frequency synthesizer. It uses a multiplication-based phase detector (PD) and a second-order active loop filter (LF). A fractional N divider is also included for frequency multiplication and synthesis. The second order active LF is defined by three parameters (ka,tau_1, tau_2). tau_1 determines the cutoff frequency and tau_2 determines the stop frequency. tau_1 should be greater than tau_2. The gain, ka, is chosen based on damping criteria. The input reference frequency, f _ref, can be multiplied up or down by setting the number of divisions, N, of the VCO output signal, f _vco. (f _vco=N·f _ref) (Figures 13.50–13.53).

Figure 13.50. Level 0 phase locked loop topology

Figure 13.51. Step response of the system, which settles at 866   MHz

Figure 13.52. Simulation showing the phase locked loop locked (top graph: reference input vs divided voltage-controlled oscillator (VCO); bottom graph: phase error voltage)

Figure 13.53. Simulation showing the phase locked loop unlocked (top graph: reference input vs divided voltage-controlled oscillator (VCO) feedback; bottom graph: phase error voltage)

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RF/IF Circuits

Hank Zumbahlen , with the engineering staff of Analog Devices, in Linear Circuit Design Handbook, 2008

The Reference Counter

In the classical integer-N synthesizer, the resolution of the output frequency is determined by the reference frequency applied to the phase detector. So, for example, if 200 kHz spacing is required (as in GSM phones), then the reference frequency must be 200 kHz. However, getting a stable 200 kHz frequency source is not easy. A sensible approach is to take a good crystal-based high frequency source and divide it down. For example, the desired frequency spacing could be achieved by starting with a 10 MHz frequency reference and dividing it down by 50. This approach is shown in the diagram in Figure 4-54.

Figure 4-54:. Using a reference counter in a PLL synthesizer

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Analog Signal Conditioning

Howard Austerlitz , in Data Acquisition Techniques Using PCs (Second Edition), 2003

3.2.3 The Phase-Locked Loop

The phase-locked loop (PLL) is an interesting device. As shown in Figure 3-11 , it consists of a phase detector, VCO, and low-pass filter. This comprises a servo loop, where the VCO is phase-locked to the input signal and oscillates at the same frequency. If there is a phase or frequency difference between the two sources, the phase detector produces an output that is used to correct the VCO. The low-pass filter is used to remove unwanted high-frequency components from the phase detector's output. One application for this device is to demodulate an FM (frequency modulated) signal.

Figure 3-11. Phase-locked loop.

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Design of Phase Detector Circuit Using Op Amp

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